Optical (or lithographic) shrink processes of standard technology nodes, so called “half node” processes, are offered by semiconductor fabrication facilities (e.g., foundries). An optical shrink technology node (“half node”) process may include a process having dimensions between technology nodes on the International Technology Roadmap for Semiconductors. Examples of typical optical shrink processes include 40, 55, 80, and 110 nanometer node processes, however any optical scaling factor may be possible. These exemplary optical shrink processes are optical shrinks of 45, 65, 90, and 130 nanometer standard technology node processes respectively. An optical shrink process includes any process that reduces the size of a circuit or chip without re-designing the circuit to fit into a smaller area. Thus, the provision of an optical shrink process allows designers to improve the performance and reduce the size of an integrated circuit. Costs can also be reduced, for example, by increasing the number of die available per wafer. Use of an optical shrink process also allows for quick realization of these design benefits using a design provided (e.g., drawn) by a standard (non-optical shrink) node as it does not require designing in a new node. In other words, a design for an integrated circuit (IC) in a standard node may be used to fabricate ICs in a smaller (shrink) technology node (e.g., a half node).
However, various actions may be required by a designer of an integrated circuit in order to ensure proper manufacturability and performance of a circuit that is to be fabricated using an optical shrink technology node. Therefore, what is desired is a design process and system that provides for decreased actions by a designer to provide a circuit in an optical shrink process.